The Xyce Parallel Electronic Simulator is a SPICE-compatible circuit simulator, developed internally at Sandia National Laboratories and funded by the National Nuclear Security Administration's Advanced Simulation and Computing (ASC) Campaign. In continuous development since 1999, Xyce is designed to run on large-scale parallel computing platforms, though it also executes efficiently on a variety of architectures, including single processor workstations. As a mature platform for large-scale parallel circuit simulation, Xyce supports standard capabilities available from commercial simulators, in addition to a variety of devices and models specific to Sandia's needs.
Xyce Electronic Simulator™ and Xyce™ are trademarks of National Technology & Engineering Solutions of Sandia, LLC (NTESS).
A goal of the Xyce development team is for Xyce to be SPICE-compatible. However, Xyce is not a derivative of SPICE. It was designed and written from scratch in C++, with modular, flexible design as a goal. Xyce also leverages Trilinos, an open-source solver library also under development at Sandia. Trilinos is an effort to develop and implement robust algorithms and enabling technologies using modern object-oriented software design, while still leveraging the value of established libraries such as PETSc, Metis/ParMetis, SuperLU, Aztec, the BLAS and LAPACK. Trilinos includes a number of circuit-specific solvers, including the KLU direct solver.
Xyce is designed and written from the ground up to support large-scale parallel computing architectures. Xyce uses a message-passing implementation (MPI), allowing it to run on serial, shared-memory and distributed-memory parallel systems. Careful attention has been paid to the specific nature of circuit-simulation problems to address optimal parallel efficiency, even as the number of processors increases. Though parallel scaling is problem-specific, Xyce has shown scalability out to hundreds of processors.
Xyce has been designed to use a differential-algebraic equation (DAE) formulation. Among other advantages, this allows the device models to be nearly independent of the analysis type, and it improves encapsulation between the models and the solver layers of the source code. In a SPICE-based code, new device functions are created for each type of analysis. With Xyce’s DAE implementation, this is not necessary. The same device load functions can be used with all analysis methods, resulting in a faster development time for new devices and new analysis types.
As a SPICE-compatible tool, Xyce supports standard analysis methods, such as steady-state (DCOP), transient (TRAN) and small-signal frequency domain (AC). A number of more exotic analysis methods have also been implemented, including Harmonic Balance, Multi-Time PDE and model-order reduction methods.
Xyce supports a canonical set of compact models. These include most SPICE3f5 models, and industry standard models, such as: VBIC and FBH bipolar transistor models, various BSIM MOSFET models, the PSP MOSFET model and the VDMOS power MOSFET model. A number of non-traditional models are also implemented that support neuron simulation and reaction networks. In addition, Verilog-A models may be processed into Xyce-compatible C++ code using the ADMS model compiler with the Xyce/ADMS back-end. Finally, a powerful expression capability is included in Xyce, allowing for the parameterization of existing models, or the implementation of user-defined behavioral models directly in the input file. The expression capability includes user-defined functions, conditional expressions and time integration, among other features.
For more information or to provide feedback, please contact the Xyce team.