Synopsys is addressing the slow verification performance of analog/mixed-signal (AMS) system-on-chip (SoC) software bring-up. Validation of software executing on pre-silicon RTL typically uses hardware emulation to increase verification performance by multiple orders of magnitude compared to software simulation. Currently, however, FPGA-based emulation doesn’t support AMS designs. Through the POSH program, Synopsys is pursuing three technologies: (1) behavioral abstraction of a SPICE netlist into a real-number model (RNM), (2) RNM emulation, (3) AMS assertion checks. Access to these techniques, including the Synopsys ZeBu emulator, is available to select POSH partners.