Trusted Silicon Stratus is currently in closed beta. Please contact us if you would like to participate.


Purdue University’s gds2Para is a layout analyzer delivering rapid and first-principles-accurate analysis of chips, packages, and boards. A novel, fast, layout inverse based solver extracts parasitics from the GDSII file into an RLC or network parameters. If the simulation is the end goal, the analyzer performs simulation directly without extraction.

Visit the gds2Para GitHub page for support.

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